/*
 *  Created on: Jun 20, 2016
 *      Author: duobao
 */

#ifndef FHXGM_H_
#define FHXGM_H_


#define DMAC0_REG_BASE          (0x00500000)
#define DMAC1_REG_BASE          (0x00510000)
#define INTC_REG_BASE           (0x00520000)
#define AES_REG_BASE            (0x00530000)

#define GIC400_REG_BASE         (0x02000000)
#define CORESIGHT_REG_BASE      (0x03000000)

#define POWER_REG_BASE          (0x04030000)

#define I2S_REG_BASE	        (0x04100000)
#define SPI0_REG_BASE	        (0x04110000)
#define SPI1_REG_BASE	        (0x04120000)
#define SPI2_REG_BASE	        (0x04130000)
#define HASH_REG_BASE	        (0x04140000)
#define TZPC_REG_BASE	        (0x04150000)
#define UART0_REG_BASE	        (0x04500000)
#define UART1_REG_BASE	        (0x04510000)
#define UART2_REG_BASE	        (0x04520000)
#define UART3_REG_BASE	        (0x04530000)
#define I2C0_REG_BASE	        (0x04540000)
#define I2C1_REG_BASE	        (0x04550000)
#define I2C2_REG_BASE	        (0x04560000)
#define I2C3_REG_BASE	        (0x04570000)
#define I2C4_REG_BASE	        (0x04580000)
#define PWM_REG_BASE	        (0x04600000)
#define STM0_REG_BASE	        (0x04610000)
#define STM1_REG_BASE	        (0x04620000)
#define WDT_REG_BASE	        (0x04630000)
#define GPIO0_REG_BASE	        (0x04640000)
#define GPIO1_REG_BASE	        (0x04650000)
#define TMR0_REG_BASE	        (0x04660000)
#define TMR1_REG_BASE	        (0x04670000)
#define GPIO2_REG_BASE	        (0x04680000)
#define GPIO3_REG_BASE	        (0x04690000)
#define ACW_REG_BASE	        (0x04700000)
#define EFUSE_REG_BASE	        (0x04710000)
#define SADC_REG_BASE	        (0x04720000)
#define RTC_REG_BASE	        (0x04750000)
#define EPHY_REG_BASE	        (0x0b020000)
#define PERF_REG_BASE	        (0x04830000)
#define TZC400_REG_BASE	        (0x04840000)

#define USBC_REG_BASE	        (0x0BE00000)
#define GMAC_REG_BASE	        (0x0BF00000)
#define SDC0_REG_BASE	        (0x04900000)
#define SDC1_REG_BASE	        (0x04A00000)

#define CPU_CTRL_REG_BASE       (0x01000000)
#define CPU_RESET_REG_BASE      (0x01010000)
#define TOP_CTRL_REG_BASE       (0x04000000)
#define CLK_REG_BASE            (0x04010000)
#define PIN_REG_BASE            (0x04020000)

#define NN_CRTL_REG_BASE        (0x0B000000)

#define REG_EPHY_BASE           (EPHY_REG_BASE)
#define REG_MDIO_BASE           (REG_EPHY_BASE + 0x600)

#define REG_PMU_USB_CFG         (NN_CRTL_REG_BASE + 0x0024)
#define REG_PMU_USB_SYS0        (NN_CRTL_REG_BASE + 0x0028)
#define REG_PMU_USB_SYS1        (NN_CRTL_REG_BASE + 0x002C)
#define REG_PMU_USB_TUNE        (NN_CRTL_REG_BASE + 0x0030)
#define REG_PMU_GMAC_REG        (NN_CRTL_REG_BASE + 0x0038)
#define REG_PMU_EPHY_SEL        (NN_CRTL_REG_BASE + 0x0044)

#define REG_PMU_ARC_INTC_MASK   (CPU_CTRL_REG_BASE + 0x0010)
#define REG_PMU_A625_START_CTRL (CPU_CTRL_REG_BASE + 0x0014)
#define REG_PMU_CPU_SYS_MISC    (CPU_CTRL_REG_BASE + 0x0018)
#define REG_PMU_DMA_HDSHAKE_EN  (CPU_CTRL_REG_BASE + 0x0020)

#define REG_PMU_WREN            (CPU_CTRL_REG_BASE + 0x0040)
#define REG_PMU_BOOT_MODE       (CPU_CTRL_REG_BASE + 0x0044)
#define REG_PMU_DDR_SIZE        (CPU_CTRL_REG_BASE + 0x0048)
#define REG_PMU_CHIP_INFO       (CPU_CTRL_REG_BASE + 0x0050)
#define REG_PMU_EPHY_PARAM      (CPU_CTRL_REG_BASE + 0x0054)
#define REG_PMU_RTC_PARAM       (CPU_CTRL_REG_BASE + 0x0058)

#define REG_PMU_A625BOOT0       (CPU_CTRL_REG_BASE + 0x0084)
#define REG_PMU_A625BOOT1       (CPU_CTRL_REG_BASE + 0x0088)
#define REG_PMU_A625BOOT2       (CPU_CTRL_REG_BASE + 0x008C)
#define REG_PMU_A625BOOT3       (CPU_CTRL_REG_BASE + 0x0090)

//reserve 14 ~ 15
#define REG_PMU_GMAC_TUNING_0   (CPU_CTRL_REG_BASE + 0x007c)
#define REG_PMU_GMAC_TUNING_1   (CPU_CTRL_REG_BASE + 0x0080)

#define REG_PMU_SCU_PLL_WREN    (CPU_CTRL_REG_BASE + 0x0)

#define REG_PMU_CHIP_ID         (TOP_CTRL_REG_BASE + 0x0000)
#define REG_PMU_IP_VER          (TOP_CTRL_REG_BASE + 0x0004)
#define REG_PMU_FW_VER          (TOP_CTRL_REG_BASE + 0x0008)

#define REG_PMU_PTSLO           (TOP_CTRL_REG_BASE + 0x001C)
#define REG_PMU_PTSHI           (TOP_CTRL_REG_BASE + 0x0020)
#define REG_PMU_USER0           (TOP_CTRL_REG_BASE + 0x0024)

#define REG_PMU_PLL1_CTRL0          (CLK_REG_BASE + 0x0000)
#define REG_PMU_PLL1_CTRL1          (CLK_REG_BASE + 0x0004)
#define REG_PMU_PLL2_CTRL0          (CLK_REG_BASE + 0x0008)
#define REG_PMU_PLL2_CTRL1          (CLK_REG_BASE + 0x000C)
#define REG_PMU_PLL3_CTRL0          (CLK_REG_BASE + 0x0010)
#define REG_PMU_PLL3_CTRL1          (CLK_REG_BASE + 0x0014)
#define REG_PMU_PLL4_CTRL0          (CLK_REG_BASE + 0x0018)
#define REG_PMU_PLL4_CTRL1          (CLK_REG_BASE + 0x001C)
#define REG_PMU_CLK_SEL0            (CLK_REG_BASE + 0x0020)
#define REG_PMU_CLK_SEL1            (CLK_REG_BASE + 0x0024)
#define REG_PMU_CLK_SEL2            (CLK_REG_BASE + 0x0028)
#define REG_PMU_CLK_GATE0           (CLK_REG_BASE + 0x002C)
#define REG_PMU_CLK_GATE1           (CLK_REG_BASE + 0x0030)
#define REG_PMU_CLK_GATE2           (CLK_REG_BASE + 0x0034)
#define REG_PMU_PRE_CLK_GATE        (CLK_REG_BASE + 0x0038)
#define REG_PMU_CLK_DIV0            (CLK_REG_BASE + 0x003C)
#define REG_PMU_CLK_DIV1            (CLK_REG_BASE + 0x0040)
#define REG_PMU_CLK_DIV2            (CLK_REG_BASE + 0x0044)
#define REG_PMU_CLK_DIV3            (CLK_REG_BASE + 0x0048)
#define REG_PMU_CLK_DIV4            (CLK_REG_BASE + 0x004C)
#define REG_PMU_CLK_DIV5            (CLK_REG_BASE + 0x0050)
#define REG_PMU_CLK_DIV6            (CLK_REG_BASE + 0x0054)
#define REG_PMU_SWRST_MAIN_CTRL0    (CLK_REG_BASE + 0x0058)
#define REG_PMU_SWRST_MAIN_CTRL1    (CLK_REG_BASE + 0x005C)
#define REG_PMU_SWRST_AHB_CTRL      (CLK_REG_BASE + 0x0060)
#define REG_PMU_SWRST_APB_CTRL      (CLK_REG_BASE + 0x0064)
#define REG_PMU_SWRSTN_NSR          (CLK_REG_BASE + 0x0068)
#define REG_PMU_SWRSTN_NSR1         (CLK_REG_BASE + 0x006C)
#define REG_PMU_DLL                 (CLK_REG_BASE + 0x0078)

#define REG_PMU_CPU_GATE            (CPU_RESET_REG_BASE + 0x0000)
#define REG_PMU_CPU_SWRST           (CPU_RESET_REG_BASE + 0x0004)

#define REG_TOP_SCU_PLL_WREN           (TOP_CTRL_REG_BASE + 0x0058)
#define REG_PMU_SDC_MISC            (TOP_CTRL_REG_BASE + 0x006C)




//todo: leave empty
#define SCU_UNLOCK SET_REG(REG_TOP_SCU_PLL_WREN,0x706c6c63)
#define SCU_LOCK   SET_REG(REG_TOP_SCU_PLL_WREN,0)

#define UART_CLOCK_FREQ         (16666667)

/* mac phy clk below */
#define CLK_SCAN_BIT_POS                (28)
#define INSIDE_PHY_ENABLE_BIT_POS       (0)
#define MAC_REF_CLK_DIV_MASK            (0x0f)
#define MAC_REF_CLK_DIV_BIT_POS         (24)
#define MAC_PAD_RMII_CLK_MASK           (0x0f)
#define MAC_PAD_RMII_CLK_BIT_POS        (24)
#define MAC_PAD_MAC_REF_CLK_BIT_POS     (28)
#define ETH_REF_CLK_OUT_GATE_BIT_POS    (25)
#define ETH_RMII_CLK_OUT_GATE_BIT_POS   (28)
#define IN_OR_OUT_PHY_SEL_BIT_POS       (28)
#define INSIDE_CLK_GATE_BIT_POS         (0)
#define INSIDE_PHY_SHUTDOWN_BIT_POS     (31)
#define INSIDE_PHY_RST_BIT_POS          (30)
#define INSIDE_PHY_TRAINING_BIT_POS     (27)
#define INSIDE_PHY_TRAINING_MASK        (0x0f)

enum DMA_HW_HS_MAP
{
    ACODEC_RX = 0,
    ACODEC_TX,
    SPI1_RX,
    SPI1_TX,
    SPI0_RX,
    SPI0_TX,
    UART0_RX,
    UART0_TX,
    UART1_RX,
    UART1_TX,
    I2S_RX,
    I2S_TX,
    UART2_RX,
    UART2_TX,
    SPI2_RX,
    SPI2_TX,
    DMA_HW_HS_END,
};


struct s_train_val{
	unsigned char *name;
	unsigned int src_add;
	unsigned int src_mask;
	unsigned int src_vaild_index;
	unsigned char *dst_base_name;
	unsigned int dst_add;
	unsigned int dst_vaild_index;
	unsigned int *bind_train_array;
	unsigned int bind_train_size;
	int usr_train_offset;
};

struct soc_reg_tuning{
    //phy id 0 ~ 24bit
    unsigned char id_l;
    unsigned char id_m;
    unsigned char id_h;
	//1000_txpol:1000_rxpol:100_txpol:100_rxpol
	unsigned char	area_pol;

	unsigned char	area_1000_txdll;
	unsigned char	area_1000_rxdll;
	unsigned char	area_100_txdll;
	unsigned char	area_100_rxdll;
};


struct gmac_plat_info{
	unsigned int regs;
	unsigned int id;
#define MAX_PHY_DRIVER_SUPPORT_SIZE	5
	char *phy_driver_list[MAX_PHY_DRIVER_SUPPORT_SIZE];
    void *p_cfg_array;
};

#define FH_GMAC_PHY_IP101G	0x02430C54
#define FH_GMAC_PHY_RTL8201	0x001CC816
#define FH_GMAC_PHY_TI83848	0xFFFFFFFF
#define FH_GMAC_PHY_INTERNAL 0x441400
#define FH_GMAC_PHY_INTERNAL_V2 0x46480000
#define FH_GMAC_PHY_RTL8211F 0x001cc916
#define FH_GMAC_PHY_MAE0621 0x7b744411
#define FH_GMAC_PHY_JL2101 0x937c4032
#define FH_GMAC_PHY_DUMMY	0xE3FFE3FF
#endif /* FHXGM_H_ */
